View STM32F101VBT6XXX_8813876.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

may 2010 doc id 13586 rev 13 1/85 1 stm32f101x8 stm32f101xb medium-density access line, arm-based 32-bit mcu with 64 or 128 kb flash, 6 timers, adc and 7 communication interfaces features core: arm 32-bit cortex?-m3 cpu ? 36 mhz maximum frequency, 1.25 dmips/mhz (dhrystone 2.1) performance at 0 wait state memory access ? single-cycle multiplication and hardware division memories ? 64 to 128 kbytes of flash memory ? 10 to 16 kbytes of sram clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr and programmable voltage detector (pvd) ? 4-to-16 mhz crystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc ? pll for cpu clock ? 32 khz oscillator for rtc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers debug mode ? serial wire debug (swd) and jtag interfaces dma ? 7-channel dma controller ? peripherals supported: timers, adc, spis, i 2 cs and usarts 1 12-bit, 1 s a/d converter (up to 16 channels) ? conversion range: 0 to 3.6 v ? temperature sensor up to 80 fast i/o ports ? 26/37/51/80 i/os, all mappable on 16 external interrupt vectors and almost all 5 v-tolerant six timers ? three 16-bit timers, each with up to 4 ic/oc/pwm or pulse counter ? 2 watchdog timers (independent and window) ? systick timer: 24-bit downcounter up to 7 communication interfaces ? up to 2 x i 2 c interfaces (smbus/pmbus) ? up to 3 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 2 spis (18 mbit/s) crc calculation unit, 96-bit unique id ecopack ? packages table 1. device summary reference part number stm32f101x8 stm32f101c8, stm32f101r8 stm32f101v8, stm32f101t8 stm32f101xb stm32f101rb, stm32f101vb, stm32f101cb stm32f101tb lqfp48 7 x 7 mm lqfp100 14 x 14 mm lqfp64 10 x 10 mm vfqfpn36 6 6 mm vfqfpn48 7 7 mm www.st.com
contents stm32f101x8, stm32f101xb 2/85 doc id 13586 rev 13 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 arm ? cortex?-m3 core with embedded flash and sram . . . . . . . . . 15 2.3.2 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.11 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 rtc (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.18 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.19 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 universal synchronous/asynchronous receiver transmitter (usart) . . 19 2.3.21 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.22 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.23 adc (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.24 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.25 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
stm32f101x8, stm32f101xb contents doc id 13586 rev 13 3/85 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33 5.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 33 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.11 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 52 5.3.12 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.13 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.14 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.15 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2.2 evaluating the maximum junction temperature for an application . . . . . 77
contents stm32f101x8, stm32f101xb 4/85 doc id 13586 rev 13 7 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
stm32f101x8, stm32f101xb list of tables doc id 13586 rev 13 5/85 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. device features and peripheral counts (stm32f101xx medium-density access line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. stm32f101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. medium-density stm32f101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 9. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 table 12. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 14. maximum current consumption in sleep mode, code running from flash or ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 38 table 16. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 42 table 18. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 21. hse 4-16 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 table 22. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 25. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 26. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 27. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 28. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 30. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 31. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 32. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 33. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 34. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 35. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 36. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 37. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 38. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 39. scl frequency (f pclk1 = 36 mhz, v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 40. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 41. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 42. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 43. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
list of tables stm32f101x8, stm32f101xb 6/85 doc id 13586 rev 13 table 44. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 45. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 46. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 71 table 47. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 72 table 48. lqpf100 ? 14 x14 mm, 100-pin low-profile quad flat package mechanical data. . . . . . . . 73 table 49. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 74 table 50. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 75 table 51. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 52. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 53. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
stm32f101x8, stm32f101xb list of figures doc id 13586 rev 13 7/85 list of figures figure 1. stm32f101xx medium-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. stm32f101xx medium-density access line lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . 21 figure 4. stm32f101xx medium-density access line lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5. stm32f101xx medium-density access line lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6. stm32f101xx medium-density access line vfqpfn48 pinout . . . . . . . . . . . . . . . . . . . . . 23 figure 7. stm32f101xx medium-density access line vfqpfn36 pinout . . . . . . . . . . . . . . . . . . . . . 23 figure 8. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled. . . . . . . . . . . . . . . . . . 37 figure 14. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled . . . . . . . . . . . . . . . . . 37 figure 15. typical current consumption on v bat with rtc on versus temperature at different v bat values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. typical current consumption in stop mode with regulator in run mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17. typical current consumption in stop mode with regulator in low-power mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. typical current consumption in standby mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 19. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 20. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 21. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 22. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 23. standard i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 24. standard i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 figure 25. 5 v tolerant i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 26. 5 v tolerant i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 27. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 28. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 29. i 2 c bus ac waveforms and measurement circuit (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 30. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 31. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 32. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 33. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 34. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 35. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 68 figure 36. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . . 69 figure 37. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package outline (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 38. recommended footprint (dimensions in mm) (1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 39. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package outline (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 40. recommended footprint (dimensions in mm) (1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 41. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 73 figure 42. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
list of figures stm32f101x8, stm32f101xb 8/85 doc id 13586 rev 13 figure 43. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 74 figure 44. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 45. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 46. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 47. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
stm32f101x8, stm32f101xb introduction doc id 13586 rev 13 9/85 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f101x8 and stm32f101xb medium-density access line microcontrollers. for more details on the whole stmicroelectronics stm32f101xx family, please refer to section 2.2: full compatib ility throughout the family . the medium-density stm32f101xx datasheet should be read in conjunction with the low-, medium- and high-density stm32f10xxx reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f10xxx flash programming manual. the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
description stm32f101x8, stm32f101xb 10/85 doc id 13586 rev 13 2 description the stm32f101xb and stm32f101x8 medium-dens ity access line family incorporates the high-performance arm cortex?-m3 32-bit risc core operating at a 36 mhz frequency, high-speed embedded memories (flash memory up to 128 kbytes and sram up to 16 kbytes), and an extensive ra nge of enhanced peri pherals and i/os c onnected to two apb buses. all devices offer standard communication interfaces (two i 2 cs, two spis, and up to three usarts), one 12-bit adc and three general-purpose 16-bit timers. the stm32f101xx medium-density access line family operates in the ?40 to +85 c temperature range, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f101xx medium-density access line fa mily includes devices in four different packages ranging from 36 pins to 100 pins. depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. these features make the stm32f101xx medium-d ensity access line microcontroller family suitable for a wide range of applications: application control and user interface medical and handheld equipment pc peripherals, gaming and gps platforms industrial applications: plc, inverters, printers, and scanners alarm systems, video intercom, and hvac figure 1 shows the general block diagram of the device family.
stm32f101x8, stm32f101xb description doc id 13586 rev 13 11/85 2.1 device overview table 2. device features and peripheral counts (stm32f101xx medium-density access line) peripheral stm32f101tx stm32f101cx stm32f101rx stm32f101vx flash - kbytes 64 128 64 128 64 128 64 128 sram - kbytes 10 16 10 16 10 16 10 16 timers general -purpose 33 3 3 communication spi 12 2 2 i 2 c 12 2 2 usart 23 3 3 12-bit synchronized adc number of channels 1 10 channels 1 10 channels 1 16 channels 1 16 channels gpios 26 37 51 80 cpu frequency 36 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient temperature: ?40 to +85 c (see ta b l e 8 ) junction temperature: ?40 to +105 c (see ta bl e 8 ) packages vfqfpn36 lqfp48, vfqfpn48 lqfp64 lqfp100
description stm32f101x8, stm32f101xb 12/85 doc id 13586 rev 13 figure 1. stm32f101xx medium-density access line block diagram 1. af = alternate function on i/o port pin. 2. t a = ?40 c to +85 c (junction temperature up to 105 c). temp sen so r pa[ 15:0] exti w w d g nvic 12bit adc1 swd 16af jtdi jtck/swclk jtms/swdio jntrst jtdo nrst v dd = 2 to 3.6v 80af pb[ 15:0] pc[15:0] ahb2 mosi,miso,sck,nss sram 2x(8x16bit) wakeup gpioa gpiob gpioc f max : 36 mhz v ss scl,sda i2c2 v ref+ gp dma tim2 tim3 xtal osc 4-16 mhz xtal 32 khz osc_in osc_out osc32_out osc32_in pll & apb 1 : f max =24 / 36 mhz pclk1 hclk clock managt pclk 2 as af as af volt. reg. 3.3v to 1.8v power backu p i nterf ace as af 16 kb rtc rc 8 mhz cortex m3 cpu usart1 usart2 spi2 7 channels back up reg scl,sda,smba l i2c1 as af rx,tx, cts, rts, usart3 v ref- pd[15:0] gpiod ahb:f max =36 mhz 4 chann els 4 chann els fclk rc 42 khz stand by iwdg @vdd @vbat por / pdr supply @vdda vdda vssa @vdda v bat ck, smartcard as af rx,tx, cts, rts, smart card as af rx,tx, cts, rts, apb2 : f max = 36 mhz nvic spi1 mosi,miso, sck,nss as af if interface @vdda supervision pvd rst int @vdd ahb2 apb2 apb 1 awu tamper-rtc pe[15:0] gpioe flash 128 kb busm atrix 64 bit inte rfac e ibus dbus pbus obl flash trace cont rol ler syst em tim4 4 channels ai14385b traceclk traced[0:3] as as sw/jtag tpiu trace/trig ck, smartcard as af
stm32f101x8, stm32f101xb description doc id 13586 rev 13 13/85 figure 2. clock tree 1. when the hsi is used as a pll clock input, the maxi mum system clock frequency t hat can be achieved is 36 mhz. 2. to have an adc conversion time of 1 s, apb2 must be at 14 mhz or 28 mhz. hse osc 4-16 mhz osc_in osc_out osc32_in osc32_out lse osc 32.768 khz hsi rc 8 mhz lsi rc 40 khz to independent watchdog (iwdg) pll x2, x3, x4 pllmul legend: mco clock output main pllxtpre /2 ..., x16 ahb prescaler /1, 2..512 /2 pllclk hsi hse apb1 prescaler /1, 2, 4, 8, 16 adc prescaler /2, 4, 6, 8 adcclk pclk1 hclk pllclk to ahb bus, core, memory and dma to tim2, 3 and 4 to adc lse lsi hsi /128 /2 hsi hse peripherals to apb1 peripheral clock enable (13 bits) enable (3 bits) p eripheral clock apb2 prescaler /1, 2, 4, 8, 16 pclk2 peripherals to apb2 peripheral clock enable (11 bits) 36 mhz max 36 mhz max to rtc pllsrc sw mco css to cortex system timer /8 clock enable (3 bits) sysclk rtcclk rtcsel[1:0] timxclk iwdgclk sysclk fclk cortex free running clock tim2,3, 4 if (apb1 prescaler =1) x1 else x2 hse = high-speed external clock signal hsi = high-speed internal clock signal lsi = low-speed internal clock signal lse = low-speed external clock signal ai15104 36 mhz max 36 mhz max
description stm32f101x8, stm32f101xb 14/85 doc id 13586 rev 13 2.2 full compatibility throughout the family the stm32f101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. in the reference manual, the stm32f101x4 and stm32f101x6 are referred to as low-density devices, the stm32f101x8 and stm32f101xb are referred to as medium-density devices, and the stm32f101xc, stm32f101xd and stm32f101xe are referred to as high-density devices. low- and high-density devices are an extension of the stm32f101x8/b devices, they are specified in the stm32f101x4/6 and stm32f101xc/d/e datasheets, respectively. low- density devices feature lower flash memory and ram capacities and a timer less. high- density devices have higher flash memory and ram capacities, and additional peripherals like fsmc and dac, while remaining fully compatible with the other members of the stm32f101xx family. the stm32f101x4, stm32f101x6, stm32f101xc, stm32f101xd and stm32f101xe are a drop-in replacement for the stm32f101x8/b medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. moreover, the stm32f101xx performance line fam ily is fully compatible with all existing stm32f101xx access line and stm32f102xx usb access line devices. table 3. stm32f101xx family pinout memory size low-density devices medium-densi ty devices high-density devices 16 kb flash 32 kb flash (1) 1. for orderable part numbers that do not show the a inte rnal code after the temperature range code (6), the reference datasheet for electrical c haracteristics is that of the st m32f101x8/b medium-density devices. 64 kb flash 128 kb flash 256 kb flash 384 kb flash 512 kb flash 4 kb ram 6 kb ram 10 kb ram 16 kb ram 32 kb ram 48 kb ram 48 kb ram 144 5 usarts 4 16-bit timers, 2 basic timers 3 spis, 2 i 2 cs, 1 adc, 2 dacs, fsmc (100 and 144 pins) 100 3 usarts 3 16-bit timers 2 spis, 2 i2cs, 1 adc 64 2 usarts 2 16-bit timers 1 spi, 1 i 2 c 1 adc 48 36
stm32f101x8, stm32f101xb description doc id 13586 rev 13 15/85 2.3 overview 2.3.1 arm ? cortex?-m3 core with embedded flash and sram the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f101xx medium-density access line family having an embedded arm core, is therefore compatible with all arm tools and software. 2.3.2 embedded flash memory 64 or 128 kbytes of embedded flash is available for storing programs and data. 2.3.3 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.3.4 embedded sram up to 16 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. 2.3.5 nested vectored interrupt controller (nvic) the stm32f101xx medium-density access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency.
description stm32f101x8, stm32f101xb 16/85 doc id 13586 rev 13 2.3.6 external interrupt /event controller (exti) the external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 cloc k period. up to 80 gp ios can be connected to the 16 external interrupt lines. 2.3.7 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an ex ternal 4-16 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resonator or oscillator). several prescalers allow the configuration of the ahb frequency, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maximum freque ncy of the ahb and the apb domains is 36 mhz. see figure 2 for details on the clock tree. 2.3.8 boot modes at startup, boot pins are used to select one of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1. for further details please refer to an2606. 2.3.9 power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.8 to 3.6 v: power supply for rtc, ex ternal clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 11: power supply scheme . 2.3.10 power supply supervisor the device has an integrated power on reset (por)/power down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remains in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher
stm32f101x8, stm32f101xb description doc id 13586 rev 13 17/85 than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. refer to table 10: embedded reset and power control block characteristics for the values of v por/pdr and v pvd . 2.3.11 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. mr is used in the nominal regulation mode (run) lpr is used in the stop mode power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode, providing high impedance output. 2.3.12 low-power modes the stm32f101xx medium-density access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output or the rtc alarm. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), a iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 2.3.13 dma the flexible 7-channel general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.
description stm32f101x8, stm32f101xb 18/85 doc id 13586 rev 13 each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general purpose timers timx and adc. 2.3.14 rtc (real-time cl ock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are ten 16-bit registers used to store 20 bytes of user application data when v dd power is not present. the real-time clock provides a set of continuo usly running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. it is clocke d by a 32.768 khz external crysta l, resonator or oscillator, the internal low power rc oscillator or the high -speed external clock divided by 128. the internal low power rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural crystal deviation. the rtc features a 32-bit programmable counter for long term measurement using the compare register to generate an alarm. a 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. 2.3.15 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 2.3.16 window watchdog the window watchdog is based on a 7-bit downcoun ter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. 2.3.17 systick timer this timer is dedicated for os, but could al so be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source 2.3.18 general-purpose timers (timx) there are three synchronizable general-purpose timers embedded in the stm32f101xx medium-density access line devices. these timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input
stm32f101x8, stm32f101xb description doc id 13586 rev 13 19/85 capture, output compare, pwm or one pulse mode output. this gives up to 12 input captures / output compares / pwms on the largest packages. the general-purpose timers can work together via the timer link feature for synchronization or event chaining. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. they all have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. 2.3.19 i 2 c bus up to two i2c bus interfaces can operate in multimaster and slave modes. they can support standard and fast modes. they support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. a hardware crc generation/verification is embedded. they can be served by dma and they support sm bus 2.0/pm bus. 2.3.20 universal sy nchronous/asynchronous receiver transmitter (usart) the available usart interfaces communicate at up to 2.25 mbit/s. they provide hardware management of the cts and rts signals, support irda sir endec, are iso 7816 compliant and have lin master/slave capability. the usart interfaces can be served by the dma controller. 2.3.21 serial perip heral interface (spi) up to two spis are able to communicate up to 18 mbit/s in slave and master modes in full- duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. both spis can be served by the dma controller. 2.3.22 gpios (genera l-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current- capable except for analog inputs. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 2.3.23 adc (analog to digital converter) the 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller.
description stm32f101x8, stm32f101xb 20/85 doc id 13586 rev 13 an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 2.3.24 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.25 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp.
stm32f101x8, stm32f101xb pinouts and pin description doc id 13586 rev 13 21/85 3 pinouts and pin description figure 3. stm32f101xx medium-den sity access line lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pe2 pe3 pe4 pe5 pe6 vbat pc14-osc32_in pc15-osc32_out vss_5 vdd_5 osc_in osc_out nrst pc0 pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p pa 1 pa 2 vdd_2 vss_2 nc pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai14386b lqfp100 pc13-tamper-rtc
pinouts and pin description stm32f101x8, stm32f101xb 22/85 doc id 13586 rev 13 figure 4. stm32f101xx medium-density access line lqfp64 pinout figure 5. stm32f101xx medium-density access line lqfp48 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc14-osc32_in pc15-osc32_out pd0 osc_in pd1 osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai14387b pc13-tamper-rtc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 lqfp48 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pb15 pb14 pb13 pb12 vbat pc14-osc32_in pc15-osc32_out pd0-osc_in pd1-osc_out nrst vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa 1 5 pa 1 4 ai14378d pc13-tamper-rtc
stm32f101x8, stm32f101xb pinouts and pin description doc id 13586 rev 13 23/85 figure 6. stm32f101xx medium-density access line vfqpfn48 pinout figure 7. stm32f101xx medium-density access line vfqpfn36 pinout ai18300 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out pd0-osc_in pd1-osc_out nrst vssa vdda pa0-wkup pa 1 pa 2 vdd_2 vss_2 pa13 pa12 pa11 pa10 pa 9 pa 8 pb15 pb14 pb13 pb12 48 vfqfpn48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 v ss_3 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 36 35 34 33 32 31 30 29 28 v dd_3 1 27 v dd_2 osc_in/pd0 2 26 v ss_2 osc_out/pd1 3 25 pa13 nrst 4 qfn36 24 pa12 v ssa 5 23 pa11 v dda 6 22 pa10 pa0-wkup 7 21 pa 9 pa 1 8 20 pa 8 pa 2 9 19 v dd_1 10 11 12 13 14 15 16 17 18 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 v ss_1 ai14654
pinouts and pin description stm32f101x8, stm32f101xb 24/85 doc id 13586 rev 13 table 4. medium-density stm32f101xx pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (3)(4) lqfp48/ vfqfpn48 lqfp64 lqfp100 vfqfpn36 default remap - - 1 - pe2 i/o ft pe2 traceclk - - 2 - pe3 i/o ft pe3 traced0 - - 3 - pe4 i/o ft pe4 traced1 - - 4 - pe5 i/o ft pe5 traced2 - - 5 - pe6 i/o ft pe6 traced3 116- v bat sv bat 227- pc13-tamper- rtc (5) i/o pc13 (6) tamper-rtc 338- pc14- osc32_in (5) i/o pc14 (6) osc32_in 449- pc15- osc32_out (5) i/o pc15 (6) osc32_out --10- v ss_5 sv ss_5 --11- v dd_5 sv dd_5 5 5 12 2 osc_in i osc_in 6 6 13 3 osc_out o osc_out 7 7 14 4 nrst i/o nrst - 8 15 - pc0 i/o pc0 adc_in10 - 9 16 - pc1 i/o pc1 adc_in11 - 10 17 - pc2 i/o pc2 adc_in12 - 11 18 - pc3 i/o pc3 adc_in13 812195 v ssa sv ssa --20- v ref- sv ref- --21- v ref+ sv ref+ 913226 v dda sv dda 10 14 23 7 pa0-wkup i/o pa0 wkup/usart2_cts (8) / adc_in0/ tim2_ch1_etr (8) 11 15 24 8 pa1 i/o pa1 usart2_rts (8) / adc_in1/tim2_ch2 (8) 12 16 25 9 pa2 i/o pa2 usart2_tx (8) / adc_in2/tim2_ch3 (8) 13 17 26 10 pa3 i/o pa3 usart2_rx (8) / adc_in3/tim2_ch4 (8) -1827- v ss_4 sv ss_4
stm32f101x8, stm32f101xb pinouts and pin description doc id 13586 rev 13 25/85 -1928- v dd_4 sv dd_4 14 20 29 11 pa4 i/o pa4 spi1_nss (8) /adc_in4 usart2_ck (8) / 15 21 30 12 pa5 i/o pa5 spi1_sck (8) /adc_in5 16 22 31 13 pa6 i/o pa6 spi1_miso (8) /adc_in6 tim3_ch1 (8) 17 23 32 14 pa7 i/o pa7 spi1_mosi (8) /adc_in7 tim3_ch2 (8) - 24 33 pc4 i/o pc4 adc_in14 - 25 34 pc5 i/o pc5 adc_in15 18 26 35 15 pb0 i/o pb0 adc_in8/tim3_ch3 (8) 19 27 36 16 pb1 i/o pb1 adc_in9/tim3_ch4 (8) 20 28 37 17 pb2 i/o ft pb2/boot1 - - 38 - pe7 i/o ft pe7 - - 39 - pe8 i/o ft pe8 - - 40 - pe9 i/o ft pe9 --41- pe10 i/oft pe10 --42- pe11 i/oft pe11 --43- pe12 i/oft pe12 --44- pe13 i/oft pe13 --45- pe14 i/oft pe14 --46- pe15 i/oft pe15 21 29 47 - pb10 i/o ft pb10 i2c2_scl/ usart3_tx (8) tim2_ch3 22 30 48 - pb11 i/o ft pb11 i2c2_sda/ usart3_rx (8) tim2_ch4 23 31 49 18 v ss_1 sv ss_1 24 32 50 19 v dd_1 sv dd_1 25 33 51 - pb12 i/o ft pb12 spi2_nss / i2c2_smba / usart3_ck (8) 26 34 52 - pb13 i/o ft pb13 spi2_sck/ usart3_cts (8) 27 35 53 - pb14 i/o ft pb14 spi2_miso/ usart3_rts (8) 28 36 54 - pb15 i/o ft pb15 spi2_mosi table 4. medium-density stm32f101xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (3)(4) lqfp48/ vfqfpn48 lqfp64 lqfp100 vfqfpn36 default remap
pinouts and pin description stm32f101x8, stm32f101xb 26/85 doc id 13586 rev 13 - - 55 - pd8 i/o ft pd8 usart3_tx - - 56 - pd9 i/o ft pd9 usart3_rx - - 57 - pd10 i/o ft pd10 usart3_ck - - 58 - pd11 i/o ft pd11 usart3_cts - - 59 - pd12 i/o ft pd12 tim4_ch1 / usart3_rts - - 60 - pd13 i/o ft pd13 tim4_ch2 - - 61 - pd14 i/o ft pd14 tim4_ch3 - - 62 - pd15 i/o ft pd15 tim4_ch4 - 37 63 - pc6 i/o ft pc6 tim3_ch1 38 64 - pc7 i/o ft pc7 tim3_ch2 39 65 - pc8 i/o ft pc8 tim3_ch3 - 40 66 - pc9 i/o ft pc9 tim3_ch4 29 41 67 20 pa8 i/o ft pa8 usart1_ck/mco 30 42 68 21 pa9 i/o ft pa9 usart1_tx (8) 31 43 69 22 pa10 i/o ft pa10 usart1_rx (8) 32 44 70 23 pa11 i/o ft pa11 usart1_cts 33 45 71 24 pa12 i/o ft pa12 usart1_rts 34 46 72 25 pa13 i/o ft jtms-swdio pa13 - - 73 - not connected 35 47 74 26 v ss_2 sv ss_2 36 48 75 27 v dd_2 sv dd_2 37 49 76 28 pa14 i/o ft jtck/swclk pa14 38 50 77 29 pa15 i/o ft jtdi tim2_ch1_etr/ pa15/ spi1_nss - 51 78 pc10 i/o ft pc10 usart3_tx - 52 79 pc11 i/o ft pc11 usart3_rx - 53 80 pc12 i/o ft pc12 usart3_ck 55812 pd0 i/oftosc_in (7) 6 6 82 3 pd1 i/o ft osc_out (7) 54 83 - pd2 i/o ft pd2 tim3_etr - - 84 - pd3 i/o ft pd3 usart2_cts - - 85 - pd4 i/o ft pd4 usart2_rts table 4. medium-density stm32f101xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (3)(4) lqfp48/ vfqfpn48 lqfp64 lqfp100 vfqfpn36 default remap
stm32f101x8, stm32f101xb pinouts and pin description doc id 13586 rev 13 27/85 - - 86 - pd5 i/o ft pd5 usart2_tx - - 87 - pd6 i/o ft pd6 usart2_rx - - 88 - pd7 i/o ft pd7 usart2_ck 39 55 89 30 pb3 i/o ft jtdo tim2_ch2 / pb3 traceswo spi1_sck 40 56 90 31 pb4 i/o ft jntrst pb4 / tim3_ch1 spi1_miso 41 57 91 32 pb5 i/o pb5 i2c1_smbal tim3_ch2 / spi1_mosi 42 58 92 33 pb6 i/o ft pb6 i2c1_scl (8) / tim4_ch1 (8) usart1_tx 43 59 93 34 pb7 i/o ft pb7 i2c1_sda (8) / tim4_ch2 (8) usart1_rx 44 60 94 35 boot0 i boot0 45 61 95 - pb8 i/o ft pb8 tim4_ch3 (8) i2c1_scl 46 62 96 - pb9 i/o ft pb9 tim4_ch4 (8) i2c1_sda - - 97 - pe0 i/o ft pe0 tim4_etr - - 98 - pe1 i/o ft pe1 47 63 99 36 v ss_3 sv ss_3 48 64 100 1 v dd_3 sv dd_3 1. i = input, o = output, s = supply, hiz= high impedance. 2. ft= 5 v tolerant. 3. function availability depends on the chosen device. for devices having reduced peripher al counts, it is always the lower number of peripherals that is included. fo r example, if a device has only one spi, tw o usarts and two timers, they will be called spi1, usart1 & usart2 and tim2 & tim 3, respectively. refer to table 2 on page 11 . 4. if several peripherals share the same i/o pin, to avoid conf lict between these alternate f unctions only one per ipheral should be enabled at a time through the peri pheral clock enable bit (in the correspondi ng rcc peripheral clock enable register). 5. pc13, pc14 and pc15 are supplied through the power switch. sinc e the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is li mited: the speed should not exc eed 2 mhz with a maximum load of 30 pf and these ios must not be used as a current source (e.g. to drive an led). 6. main function after the first backup domain power-up. later on, it depends on the contents of the backup registers even after reset (because these registers are not reset by the main reset). for details on how to manage these ios, refer to the battery backup domain and bkp register description sections in the stm32f10xxx reference manual, available from the stmicroelectronics website: www.st.com. 7. the pins number 2 and 3 in the vfqfpn36 package, and 5 and 6 in the lqfp48 and lqfp64 packages are configured as osc_in/osc_out after reset, however the functionality of pd0 and pd1 can be remapped by software on these pins. for the lqfp100 package, pd0 and pd1 are avai lable by default, so there is no need for remapping. for more details, refer to the alternate function i/o and debug configuration section in the stm32f10xxx reference manual. the use of pd0 and pd1 in output mode is limited as they can only be used at 50 mhz in output mode. 8. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug configur ation section in the stm32f10x xx reference manual, available from the stmicroelectroni cs website: www.st.com. table 4. medium-density stm32f101xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (3)(4) lqfp48/ vfqfpn48 lqfp64 lqfp100 vfqfpn36 default remap
memory mapping stm32f101x8, stm32f101xb 28/85 doc id 13586 rev 13 4 memory mapping the memory map is shown in figure 8 . figure 8. memory map 1k apb memory space dma rtc wwdg iwdg spi2 usart2 usart3 adc1 usart1 spi1 1k 35k 1k 1k 2k 1k 1k 2k 1k 1k 1k 1k 1k 7k 1k port e 1k 1k 1k 3k 1k 1k 1k 1k 1k 1k 1k 1k 2k 1k 1k 1k i2c2 exti rcc 1k 1k 1k 1k 1k 1k 1k 1k 3k 1k 3k 1k 4k 0 1 2 3 4 5 6 7 peripherals sram reserved reserved option bytes reserved 0x4000 0000 0x4000 0400 0x4000 0800 0x4000 0c00 0x4000 2800 0x4000 2c00 0x4000 3000 0x4000 3400 0x4000 3800 0x4000 3c00 0x4000 4400 0x4000 4800 0x4000 4c00 0x4000 5400 0x4000 5800 0x4000 5c00 0x4000 6000 0x4000 6400 0x4000 6800 0x4000 6c00 0x4000 7000 0x4000 7400 0x4001 0000 0x4001 0400 0x4001 0800 0x4001 0c00 0x4001 1000 0x4001 1400 0x4001 1800 0x4001 1c00 0x4001 2400 0x4001 2800 0x4001 2c00 0x4001 3000 0x4001 3400 0x4001 3800 0x4001 3c00 0x4002 0000 0x4002 0400 0x4002 1000 0x4002 1400 0x4002 2000 0x4002 2400 0x4002 3000 0x4002 3400 0x6000 0000 0xe010 0000 0xffff ffff reserved reserved reserved crc reserved reserved flash interface reserved reserved reserved reserved reserved reserved reserved port d port c port b port a afio pwr bkp reserved reserved reserved reserved i2c1 reserved reserved reserved reserved tim4 tim3 tim2 0xffff ffff 0xe010 0000 0xe000 0000 0xc000 0000 0xa000 0000 0x8000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 0x1fff ffff 0x1fff f80f 0x1fff f800 0x1fff f000 0x0801 ffff 0x0800 0000 system memory flash memory cortex-m3 internal peripherals ai14379d 0x0000 0000 aliased to flash or system memory depending on boot pins
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 29/85 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ? ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2v ? v dd ? 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ? ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 .
electrical characteristics stm32f101x8, stm32f101xb 30/85 doc id 13586 rev 13 5.1.6 power supply scheme figure 11. power supply scheme caution: in figure 11 , the 4.7 f capacitor must be connected to v dd3 . figure 9. pin loading conditions figure 10. pin input voltage ai14123b c = 50 pf stm32f10xxx pin ai14124b stm32f10xxx pin v in ai14125d v dd 1/2/3/4/5 an alo g: rcs, pll, ... po wer swi tch v bat gp i/o s out in kernel logic (cpu, digital & memories) backup circuitry (osc32k,rtc, backup registers) wake-up logic 5 100 nf + 1 4.7 f 1.8-3.6v regulator v ss 1/2/3/4/5 v dda v ref+ v ref- v ssa adc level shifter io logic v dd 10 nf + 1 f v ref 10 nf + 1 f v dd
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 31/85 5.1.7 current con sumption measurement figure 12. current consumption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 5: voltage characteristics , table 6: current characteristics , and table 7: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 v bat v dd v dda i dd _v bat i dd table 5. voltage characteristics symbol ratings min max unit v dd ?? v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connec ted to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five volt tolerant pin (2) 2. i inj(pin) must never be exceeded (see table 6: current characteristics ). this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v in max while a negative injection is induced by v in electrical characteristics stm32f101x8, stm32f101xb 32/85 doc id 13586 rev 13 5.3 operating conditions 5.3.1 general operating conditions table 6. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin ? 25 i inj(pin) (2)(3) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 33/85 5.3.2 operating conditions at power-up / power-down subject to general operating conditions for t a . table 9. operating conditions at power-up / power-down 5.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 1 0 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . p d power dissipation at t a = 85 c (3) lqfp100 434 mw lqfp64 444 lqfp48 363 vfqfpn36 1110 t a ambient temperature maximum power dissipation ?40 85 c low power dissipation (4) ?40 105 c t j junction temperature range ?40 105 c 1. when the adc is used, refer to table 41: adc characteristics . 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and operation. 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 76 ). 4. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 76 ). table 8. general operating conditions (continued) symbol parameter co nditions min max unit symbol parameter conditions min max unit t vdd v dd rise time rate 0 ? s/v v dd fall time rate 20 ?
electrical characteristics stm32f101x8, stm32f101xb 34/85 doc id 13586 rev 13 . table 10. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis 100 mv v por/pdr power on/power down reset threshold falling edge 1.8 (1) 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (2) pdr hysteresis 40 mv t rsttempo (2) 2. guaranteed by design, not tested in production. reset temporization 1.5 2.5 4.5 ms
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 35/85 5.3.4 embedded reference voltage the parameters given in ta bl e 1 1 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . 5.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 12: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if it is explicitly mentioned the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 36 mhz) prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk/2 , f pclk2 = f hclk the parameters given in ta bl e 1 2 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . table 11. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 5.1 17.1 (2) 2. guaranteed by design, not tested in production. s v rerint (2) internal reference voltage spread over the temperature range v dd = 3 v 10 mv 10 mv t coeff (2) temperature coefficient 100 ppm/ c
electrical characteristics stm32f101x8, stm32f101xb 36/85 doc id 13586 rev 13 table 12. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. based on characterization , not tested in production. unit t a = 85 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 28.6 ma 24 mhz 19.9 16 mhz 14.7 8 mhz 8.6 external clock (4) , all peripherals disabled 36 mhz 19.8 24 mhz 13.9 16 mhz 10.7 8 mhz 6.8 table 13. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max, f hclk max. unit t a = 85 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 24 ma 24 mhz 17.5 16 mhz 12.5 8 mhz 7.5 external clock (2) all peripherals disabled 36 mhz 16 24 mhz 11.5 16 mhz 8.5 8 mhz 5.5
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 37/85 figure 13. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled figure 14. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled 0 5 10 15 20 25 -40 0 25 70 85 temperature (c) consumption (ma) 36mhz 16mhz 8mhz 0 2 4 6 8 10 12 14 16 -40 0 25 70 85 temperature (c) consumption (ma) 36mhz 16mhz 8mhz
electrical characteristics stm32f101x8, stm32f101xb 38/85 doc id 13586 rev 13 table 14. maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. unit t a = 85 c i dd supply current in sleep mode external clock (2) all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 15.5 ma 24 mhz 11.5 16 mhz 8.5 8 mhz 5.5 external clock (2) , all peripherals disabled 36 mhz 5 24 mhz 4.5 16 mhz 4 8 mhz 3 table 15. typical and maximum current consumptions in stop and standby modes symbol parameter conditions typ (1) max unit v dd /v bat = 2.0 v v dd / v bat = 2.4 v v dd /v bat = 3.3 v t a = 85 c (2) i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) - 23.5 24 200 a regulator in low-power mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) - 13.5 14 180 supply current in standby mode low-speed internal rc oscillator and independent watchdog on -2.63.4- low-speed internal rc oscillator on, independent watchdog off -2.43.2- low-speed internal rc oscillator and independent watchdog off, low-speed oscillator and rtc off -1.724 i dd_vbat backup domain supply current low-speed oscillator and rtc on 0.9 1.1 1.4 1.9 1. typical values are measured at t a = 25 c. 2. based on characterization, not rested in production.
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 39/85 figure 15. typical current consumption on v bat with rtc on versus temperature at different v bat values figure 16. typical current consumption in stop mode with regulator in run mode versus temperature at v dd = 3.3 v and 3.6 v 0 0.5 1 1.5 2 2.5 ?40 c 25 c 70 c 8 5 c 105 c temper a t u re (c) con su mption ( a ) 2 v 2.4 v 3 v 3 .6 v a i17 3 51 0 20 40 60 80 100 120 140 -45 25 70 90 temperature (c) consumption (a) 3.3 v 3.6 v
electrical characteristics stm32f101x8, stm32f101xb 40/85 doc id 13586 rev 13 figure 17. typical current consumption in stop mode with regulator in low-power mode versus temperature at v dd = 3.3 v and 3.6 v figure 18. typical current consumption in standby mode versus temperature at v dd = 3.3 v and 3.6 v 0 10 20 30 40 50 60 70 80 90 100 ?45 c 25 c 85 c temperature (c) consumption (a) 3.3 v 3.6 v 0 0.5 1 1.5 2 2.5 3 -45 25 70 90 temperature (c) consumption (a) 3.3 v 3.6 v
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 41/85 typical current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if it is explicitly mentioned the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 36 mhz) prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk/4 , f pclk2 = f hclk/2 , f adcclk = f pclk2 /4 the parameters given in ta bl e 1 6 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . table 16. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. typ (1) unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in run mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 19 14.8 ma 24 mhz 12.9 10.1 16 mhz 9.3 7.4 8 mhz 5.5 4.6 4 mhz 3.3 2.8 2 mhz 2.2 1.9 1 mhz 1.6 1.45 500 khz 1.3 1.25 125 khz 1.08 1.06 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 36 mhz 18.3 14.1 24 mhz 12.2 9.5 16 mhz 8.5 6.8 8 mhz 4.9 4 4 mhz 2.7 2.2 2 mhz 1.6 1.4 1 mhz 1.02 0.9 500 khz 0.73 0.67 125 khz 0.5 0.48
electrical characteristics stm32f101x8, stm32f101xb 42/85 doc id 13586 rev 13 table 17. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. typ (1) unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in sleep mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 7.6 3.1 ma 24 mhz 5.3 2.3 16 mhz 3.8 1.8 8 mhz 2.1 1.2 4 mhz 1.6 1.1 2 mhz 1.3 1 1 mhz 1.11 0.98 500 khz 1.04 0.96 125 khz 0.98 0.95 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 36 mhz 7 2.5 24 mhz 4.8 1.8 16 mhz 3.2 1.2 8 mhz 1.6 0.6 4 mhz 1 0.5 2 mhz 0.72 0.47 1 mhz 0.56 0.44 500 khz 0.49 0.42 125 khz 0.43 0.41
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 43/85 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 1 8 . the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature and v dd supply voltage conditions summarized in ta bl e 5 . 5.3.6 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 1 9 result from tests performed using an high-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in ta b l e 8 . table 18. peripheral current consumption peripheral typical consumption at 25 c (1) 1. f hclk = 36 mhz, f apb1 = f hclk /2, f apb2 = f hclk , default prescaler value for each peripheral. unit apb1 tim2 0.6 ma tim3 0.6 tim4 0.6 spi2 0.08 usart2 0.21 usart3 0.21 i2c1 0.18 i2c2 0.18 apb2 gpio a 0.21 gpio b 0.21 gpio c 0.21 gpio d 0.21 gpio e 0.21 adc1 (2) 2. specific conditions for adc: f hclk = 28 mhz, f apb1 = f hclk /2, f apb2 = f hclk , f adcclk = f apb2 /2, adon bit in the adc_cr2 register is set to 1. 1.4 spi1 0.24 usart1 0.35
electrical characteristics stm32f101x8, stm32f101xb 44/85 doc id 13586 rev 13 low-speed external user clock generated from an external source the characteristics given in ta b l e 2 0 result from tests performed using an low-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in ta b l e 8 . table 19. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 1825mhz v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 16 ns t r(hse) t f(hse) osc_in rise or fall time (1) 20 c in(hse) osc_in input capacitance (1) 5pf ducy (hse) duty cycle 45 55 % i l osc_in input leakage current v ss ? v in ? v dd 1 a table 20. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 ns t r(lse) t f(lse) osc32_in rise or fall time (1) 50 c in(lse) osc32_in input capacitance (1) 5pf ducy (lse) duty cycle 30 70 % i l osc32_in input leakage current v ss ? v in ? v dd 1 a
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 45/85 figure 19. high-speed external clock source ac timing diagram figure 20. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 16 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 1 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai14127b os c _i n external stm32f10xxx clock source v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel ai14140c osc32_in external stm32f10xxx clock source v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel
electrical characteristics stm32f101x8, stm32f101xb 46/85 doc id 13586 rev 13 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 21 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available fr om the st website www.st.com. figure 21. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 2 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal table 21. hse 4-16 mhz oscillator characteristics (1)(2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization , not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 8 16 mhz r f feedback resistor 200 k ? c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 ?? 30 pf i 2 hse driving current v dd = 3.3 v, v in = v ss with 30 pf load 1ma g m oscillator transconductance startup 25 ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized 2 ms ai14128b osc_ou t osc_in f hse c l1 r f stm32f10xxx 8 mh z resonator resonator with integrated capacitors bias controlled gain r ext (1) c l2
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 47/85 resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for c l1 and c l2 it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l ? 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 22. typical application with a 32.768 khz crystal table 22. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. based on characterization , not tested in production. symbol parameter conditions min typ max unit r f feedback resistor 5 m ? c (2) 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value for example msiv-tin32.768 khz. refer to crystal manufacturer for more details r s = 30 k ? 15 pf i 2 lse driving current v dd = 3.3 v v in = v ss 1.4 a g m oscillator transconductance 5 a/v t su(lse) (4) 4. t su(lse) is the startup time measured from the mom ent it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard cr ystal resonator and it can vary significantly with t he crystal manufacturer startup time v dd is stabilized 3 s ai14129b osc32_ou t osc32_in f lse c l1 r f stm32f10xxx 32.768 kh z resonator resonator with integrated capacitors bias controlled gain c l2
electrical characteristics stm32f101x8, stm32f101xb 48/85 doc id 13586 rev 13 5.3.7 internal clock source characteristics the parameters given in ta bl e 2 3 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator wakeup time from low-power mode the wakeup times given in ta b l e 2 5 are measured on a wakeup phase with an 8-mhz hsi rc oscillator. the clock source used to wake up the device depends from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. table 23. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibration? available from the st website www.st.com. 1 (3) 3. guaranteed by design, not tested in production. % factory- calibrated (4) 4. based on characterization , not tested in production. t a = ?40 to 105 c ?2 2.5 % t a = ?10 to 85 c ?1.5 2.2 % t a = 0 to 70 c ?1.3 2 % t a = 25 c ?1.1 1.8 % t su(hsi) (4) hsi oscillator startup time 12s i dd(hsi) (4) hsi oscillator power consumption 80 100 a table 24. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 85 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization , not tested in production. frequency 30 40 60 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time 85 s i dd(lsi) (3) lsi oscillator power consumption 0.65 1.2 a
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 49/85 all timings are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta bl e 8 . 5.3.8 pll characteristics the parameters given in ta bl e 2 6 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . 5.3.9 memory characteristics flash memory the characteristics are given at t a = ?40 to 85 c unless otherwise specified. table 25. low-power mode wakeup timings symbol parameter typ unit t wusleep (1) 1. the wakeup times are measured from the wakeup even t to the point at which the user application code reads the first instruction. wakeup from sleep mode 1.8 s t wustop (1) wakeup from stop mode (regulator in run mode) 3.6 s wakeup from stop mode (regu lator in low-power mode) 5.4 t wustdby (1) wakeup from standby mode 50 s table 26. pll characteristics symbol parameter value unit min (1) typ max (1) 1. based on device characteriza tion, not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 18.025mhz pll input clock duty cycle 40 60 % f pll_out pll multiplier output clock 16 36 mhz t lock pll lock time 200 s jitter cycle-to-cycle jitter 300 ps table 27. flash memory characteristics symbol parameter conditions min (1) typ max (1) unit t prog 16-bit programming time t a ??? ?40 to +85 c 40 52.5 70 s t erase page (1 kb) erase time t a ?? ?40 to +85 c 20 40 ms t me mass erase time t a ?? ?40 to +85 c 20 40 ms
electrical characteristics stm32f101x8, stm32f101xb 50/85 doc id 13586 rev 13 table 28. flash memory endurance and data retention 5.3.10 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 2 9 . they are based on the ems levels and classes defined in application note an1709. i dd supply current read mode f hclk = 36 mhz with 1 wait state, v dd = 3.3 v 20 ma write / erase modes f hclk = 36 mhz, v dd = 3.3 v 5ma power-down mode / halt, v dd = 3.0 to 3.6 v 50 a v prog programming voltage 2 3.6 v 1. guaranteed by design, not tested in production. symbol parameter conditions value unit min (1) 1. based on characterization not tested in production. typ max n end endurance t a = ?40 c to 85 c 10 kcycles t ret data retention t a = 85 c, 1 kcycle (2) 2. cycling performed over t he whole temperature range. 30 ye a r s t a = 55 c, 10 kcycle (2) 20 table 27. flash memory characteristics (continued) symbol parameter conditions min (1) typ max (1) unit
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 51/85 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and pre qualification tests in rela tion with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec61967-2 standard which specifies the test board and the pin loading. table 29. ems characteristics symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, t a ?? +25 c, f hclk ? 36 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, t a ?? +25 c, f hclk ?? 36 mhz conforms to iec 61000-4-4 4a table 30. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/36 mhz s emi peak level v dd ?? 3.3 v, t a ?? 25 c, lqfp100 package compliant with iec 61967-2 0.1 mhz to 30 mhz 7 dbv 30 mhz to 130 mhz 8 130 mhz to 1ghz 13 sae emi level 3.5 -
electrical characteristics stm32f101x8, stm32f101xb 52/85 doc id 13586 rev 13 5.3.11 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78 ic latch-up standard. 5.3.12 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 3 3 are derived from tests performed under the conditions summarized in ta b l e 8 . all i/os are cmos and ttl compliant. table 31. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c conforming to jesd22-c101 ii 500 table 32. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +85 c conforming to jesd78a ii level a
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 53/85 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 23 and figure 24 for standard i/os, and in figure 25 and figure 26 for 5 v tolerant i/os. table 33. i/o static characteristics symbol parameter conditions min typ max unit v il standard i/o input low level voltage ?0.5 0.28 (v dd ?2)+0.8 v i/o ft (1) input low level voltage ?0.5 0.32 (v dd ?2)+0.75 v ih standard i/o input high level voltage 0.41 (v dd ?2)+1.3 v dd +0.5 i/o ft (1) input high level voltage 0.42 (v dd ?2)+1 5.5 v hys standard io schmitt trigger voltage hysteresis (2) 200 mv io ft schmitt trigger voltage hysteresis (2) 5% v dd (3) mv i lkg input leakage current (4) v ss ? v in ? v dd standard i/os ? 1 a v in = 5 v i/o ft 3 r pu weak pull-up equivalent resistor (5) v in ?? v ss 30 40 50 k ? r pd weak pull-down equivalent resistor (5) v in ?? v dd 30 40 50 k ? c io i/o pin capacitance 5 pf 1. ft = 5v tolerant. to sustain a voltage higher than v dd +0.5 the internal pull-up/pull- down resistors must be disabled. 2. hysteresis voltage between schmitt trigger switching levels. based on characteriza tion, not tested in production. 3. with a minimum of 100 mv. 4. leakage could be higher than max. if negativ e current is injected on adjacent pins. 5. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order) .
electrical characteristics stm32f101x8, stm32f101xb 54/85 doc id 13586 rev 13 figure 23. standard i/o input characteristics - cmos port figure 24. standard i/o input characteristics - ttl port a i17277 b v dd (v) 1. 3 0. 8 2 3 .6 inp u t r a nge not g ua r a nteed 1.59 1 2.7 v ih =0.41(v dd -2)+1. 3 3 0.7 cmo s s t a nd a rd re qu irement v ih =0.65v dd 3 . 3 v ih /v il (v) cmo s s t a nd a rd re qu irement v il =0. 3 5v dd v il = 0.2 8 (v dd ?2)+0. 8 1.25 1.96 1.71 1.71 1.59 1 1.08 1.08 v ilm a x v ihmin ai )nputrange notguaranteed 6 )( 6 ), 6 44,requirements 6 )( 6 6 )( 6 $$ 6 ), 6 $$ 44,requirements 6 ), 6 6 $$ 6 7 ),max 7 )(min
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 55/85 figure 25. 5 v tolerant i/o input characteristics - cmos port figure 26. 5 v tolerant i/o input characteristics - ttl port output driving current the gpios (general-purpose inputs/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 6 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 6 ). 6$$ #-/3standardrequirements6 )( 6 $$ #-/3standardrequirment6 ), 6 $$ 6 )( 6 ), 6 6 $$ 6 )nputrange notguaranteed aib 6 )( 6 $$ 6 ), 6 $$ notguaranteed )nputrange 44,requirement6 )( 6 6 )(
6 $$ 6 ),
6 $$ 44,requirements6 ), 6 6 )( 6 ), 6 6 $$ 6 7 ),max 7 )(min ai
electrical characteristics stm32f101x8, stm32f101xb 56/85 doc id 13586 rev 13 output voltage levels unless otherwise specified, the parameters given in ta bl e 3 4 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . all i/os are cmos and ttl compliant. table 34. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 6 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at the same time ttl port, i io = +8 ma, 2.7 v < v dd < 3.6 v 0.4 v v oh (2) 2. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 6 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time cmos port i io = +8 ma 2.7 v < v dd < 3.6 v 0.4 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at the same time 2.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +20 ma (3) 2.7 v < v dd < 3.6 v 3. based on characterization data, not tested in production. 1.3 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?1.3 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +6 ma (3) 2 v < v dd < 2.7 v 0.4 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 57/85 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 27 and ta bl e 3 5 , respectively. unless otherwise specified, the parameters given in ta bl e 3 5 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . table 35. i/o ac characteristics (1) 1. the i/o speed is configured using th e modex[1:0] bits. refer to the stm32f10xxx reference manual for a description of gpio port configuration register. modex [1:0] bit value (1) symbol parameter conditions max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 27 . c l = 50 pf, v dd = 2 v to 3.6 v 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) 3. guaranteed by design, not tested in production. ns t r(io)out output low to high level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to high level rise time 25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 ns
electrical characteristics stm32f101x8, stm32f101xb 58/85 doc id 13586 rev 13 figure 27. i/o ac characteristics definition 5.3.13 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 3 3 ). unless otherwise specified, the parameters given in ta bl e 3 6 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 8 . figure 28. recommended nrst pin protectio n 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 36 . otherwise the reset will not be taken into account by the device. ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) ?? 2/3)t and if the duty cycle is (45-55%) ? 10 % 50% 90% when loaded by 50pf t t r(io)out table 36. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 0.8 v v ih(nrst) (1) nrst input high level voltage 2 v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true re sistance in series with a switc hable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . v in ?? v ss 30 40 50 k ? v f(nrst) (1) nrst input filtered pulse 100 ns v nf(nrst) (1) nrst input not filtered pulse 300 ns a i141 3 2d s tm 3 2f10x r pu nr s t (2) v dd filter intern a l re s et 0.1 f extern a l re s et circ u it (1)
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 59/85 5.3.14 tim time r characteristics the parameters given in ta bl e 3 7 are guaranteed by design. refer to section 5.3.12: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). 5.3.15 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 3 8 are derived from tests performed under the ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta bl e 8 . the stm32f101xx medium-density access line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: t he i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 3 8 . refer also to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 37. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1 t timxclk f timxclk = 36 mhz 27.8 ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 36 mhz 018mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk f timxclk = 36 mhz 0.0278 1820 s t max_count maximum possible count 65536 65536 t timxclk f timxclk = 36 mhz 119.2 s
electrical characteristics stm32f101x8, stm32f101xb 60/85 doc id 13586 rev 13 table 38. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be higher than 2 mhz to achieve standard mode i 2 c frequencies. it must be higher than 4 mhz to achieve fast mode i 2 c frequencies. it must be a multiple of 10 mhz to reach the 400 khz maximum i2c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 0 (4) 4. the device must internally provide a hold time of at least 300 ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 61/85 figure 29. i 2 c bus ac waveforms and measurement circuit (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 39. scl frequency (f pclk1 = 36 mhz, v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of ? 5%. for other speed ranges, the tolerance on the achieved speed ? 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k ? 400 0x801e 300 0x8028 200 0x803c 100 0x00b4 50 0x0168 20 0x0384 a i141 33 d s t a rt s da 100 4.7k i2c bus 4.7k 100 v dd v dd s tm 3 2f10x s da s cl t f( s da) t r( s da) s cl t h( s ta) t w( s clh) t w( s cll) t su ( s da) t r( s cl) t f( s cl) t h( s da) s t a rt repe a ted s t a rt t su ( s ta) t su ( s to) s top t su ( s to: s ta)
electrical characteristics stm32f101x8, stm32f101xb 62/85 doc id 13586 rev 13 spi interface characteristics unless otherwise specified, the parameters given in ta bl e 4 0 are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 8 . refer to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 40. spi characteristics (1) 1. remapped spi1 characteristics to be determined. symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 0 18 mhz slave mode 0 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 8 ns t su(nss) (2) 2. based on characterization , not tested in production. nss setup time slave mode 4 t pclk t h(nss) (2) nss hold time slave mode 73 t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f pclk = 36 mhz, presc = 4 50 60 t su(mi) (2) data input setup time master mode spi1 1 spi2 5 t su(si) (2) data input setup time slave mode 1 t h(mi) (2) data input hold time master mode spi1 1 spi2 5 t h(si) (2) data input hold time slave mode 3 t a(so) (2)(3) 3. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 36 mhz, presc = 4 055 slave mode, f pclk = 24 mhz 0 4 t pclk t dis(so) (2)(4) 4. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 10 t v(so) (2)(1) data output valid time slave mode (after enable edge) 25 t v(mo) (2)(1) data output valid time master mode (after enable edge) 3 t h(so) (2) data output hold time slave mode (after enable edge) 25 t h(mo) (2) master mode (after enable edge) 4
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 63/85 figure 30. spi timing diagram - slave mode and cpha = 0 figure 31. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
electrical characteristics stm32f101x8, stm32f101xb 64/85 doc id 13586 rev 13 figure 32. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 65/85 5.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 4 1 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 8 . note: it is recommended to perform a calibration after each power-up. table 41. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 3.6 v v ref+ positive reference voltage 2.4 v dda v i vref current on the v ref input pin 160 (1) 220 (1) a f adc adc clock frequency 0.6 14 mhz f s (2) sampling rate 0.05 1 mhz f trig (2) external trigger frequency f adc = 14 mhz 823 khz 17 1/f adc v ain conversion voltage range (3) 0 (v ssa or v ref- tied to ground) v ref+ v r ain (2) external input impedance see equation 1 and ta b l e 4 2 for details 50 k ? r adc (2) sampling switch resistance 1 k ? c adc (2) internal sample and hold capacitor 8pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc t lat (2) injection trigger conversion latency f adc = 14 mhz 0.214 s 3 (4) 1/f adc t latr (2) regular trigger conversion latency f adc = 14 mhz 0.143 s 2 (4) 1/f adc t s (2) sampling time f adc = 14 mhz 0.107 17.1 s 1.5 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. based on characterization results, not tested in production. 2. guaranteed by design, not tested in production. 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 3: pinouts and pin description for further details. 4. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 41 .
electrical characteristics stm32f101x8, stm32f101xb 66/85 doc id 13586 rev 13 equation 1: r ain max formula: the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 42. r ain max for f adc = 14 mhz (1) 1. guaranteed by design, not tested in production. t s (cycles) t s (s) r ain max (k ? ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na table 43. adc accuracy - limited test conditions (1) (2) 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and ? i inj(pin) in section 5.3.12 does not affect the adc accuracy. symbol parameter test conditions typ max (3) 3. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 28 mhz, f adc = 14 mhz, r ain < 10 k ? , v dda = 3 v to 3.6 v t a = 25 c measurements made after adc calibration 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 r ain t s f adc c adc 2 n2 + ?? ln ? ? ------------------------------------------------------------- - r adc ? ?
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 67/85 figure 33. adc accura cy characteristics table 44. adc accuracy (1) (2) (3) 1. adc dc accuracy values are m easured after internal calibration. 2. better performance could be achieved in restricted v dd , frequency, v ref and temperature ranges. 3. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and ? i inj(pin) in section 5.3.12 does not affect the adc accuracy. symbol parameter test conditions typ max (4) 4. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 28 mhz, f adc = 14 mhz, r ain < 10 k ? , v dda = 2.4 v to 3.6 v measurements made after adc calibration 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal =
electrical characteristics stm32f101x8, stm32f101xb 68/85 doc id 13586 rev 13 figure 34. typical connection diagram using the adc 1. refer to table 41 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 35 or figure 36 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 35. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref- inputs are available only on 100-pin packages. ai14139d stm32f10xxx v dd ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc (1) c adc (1) 12-bit converter sample and hold adc converter v ref+ stm32f10xxx v dda v ssa /v ref- 1 f // 10 nf 1 f // 10 nf ai14380b
stm32f101x8, stm32f101xb electrical characteristics doc id 13586 rev 13 69/85 figure 36. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref- inputs are available only on 100-pin packages. 5.3.17 temperature sen sor characteristics v ref+ /v dda stm32f10xxx 1 f // 10 nf v ref? /v ssa ai14381b table 45. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by characterizati on, not tested in production. v sense linearity with temperature ? 1 ? 2 c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 (1) voltage at 25c 1.34 1.43 1.52 v t start (2) 2. guaranteed by design, not tested in production. startup time 4 10 s t s_temp (3)(2) 3. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 s
package characteristics stm32f101x8, stm32f101xb 70/85 doc id 13586 rev 13 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stm32f101x8, stm32f101xb package characteristics doc id 13586 rev 13 71/85 1. drawing is not to scale. 2. the back-side pad is not inte rnally connected to the v ss or v dd power pads. 3. there is an exposed die pad on the underside of the vfqfpn package. it should be soldered to the pcb. all leads should also be soldered to the pcb. it is recommended to connect it to v ss . figure 37. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package outline (1) figure 38. recommended footprint (dimensions in mm) (1)(2)(3) s e a ting pl a ne c a 3 a1 a2 a ddd c pin no. 1 id r = 0.20 bottom view 1 4 8 e e l l 12 1 3 d2 b 24 25 b e2 3 6 3 7 e d v0_me 0.50 7.30 0.75 5.80 5.80 6.20 6.20 5.60 5.60 13 1 24 37 ai15799 12 48 36 25 0.55 0.30 0.20 table 46. vfqfpn48 7 x 7 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.800 0.900 1.000 0.0315 0.0354 0.0394 a1 0.020 0.050 0.0008 0.0020 a2 0.650 1.000 0.0256 0.0394 a3 0.250 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 d 6.850 7.000 7.150 0.2697 0.2756 0.2815 d2 2.250 4.700 5.250 0.0886 0.1850 0.2067 e 6.850 7.000 7.150 0.2697 0.2756 0.2815 e2 2.250 4.700 5.250 0.0886 0.1850 0.2067 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f101x8, stm32f101xb 72/85 doc id 13586 rev 13 1. drawing is not to scale. 2. the back-side pad is not inte rnally connected to the v ss or v dd power pads. 3. there is an exposed die pad on the underside of the vfqfpn package. it should be soldered to the pcb. all leads should also be soldered to the pcb. figure 39. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package outline (1) figure 40. recommended footprint (dimensions in mm) (1)(2)(3) seating plane ddd c c a3 a1 a a2 pin # 1 id r = 0.20 zr_me e2 b 19 10 18 27 28 36 19 d2 e d e l 0.30 6.30 0.50 1.00 4.30 4.30 4.80 4.80 4.10 4.10 1 28 9 19 ai14870b 36 27 18 10 0.75 table 47. vfqfpn36 6 x 6 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.800 0.900 1.000 0.0315 0.0354 0.0394 a1 0.020 0.050 0.0008 0.0020 a2 0.650 1.000 0.0256 0.0394 a3 0.250 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 d 5.875 6.000 6.125 0.2313 0.2362 0.2411 d2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 5.875 6.000 6.125 0.2313 0.2362 0.2411 e2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 l 0.350 0.550 0.750 0.0138 0.0217 0.0295 ddd 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f101x8, stm32f101xb package characteristics doc id 13586 rev 13 73/85 figure 41. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package outline (1) figure 42. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 table 48. lqpf100 ? 14 x14 mm, 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.2 0.0035 0.0079 d 15.80 16.00 16.2 0.622 0.6299 0.6378 d1 13.80 14.00 14.2 0.5433 0.5512 0.5591 d3 12.00 0.4724 e 15.80 16.00 16.2 0.622 0.6299 0.6378 e1 13.80 14.00 14.2 0.5433 0.5512 0.5591 e3 12.00 0.4724 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 0 3.5 7 0.0 3.5 7.0 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f101x8, stm32f101xb 74/85 doc id 13586 rev 13 figure 43. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline (1) figure 44. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. a a2 a1 c l1 l e e1 d d1 e b ai14398b 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 49. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0. 0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 ? 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n64 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f101x8, stm32f101xb package characteristics doc id 13586 rev 13 75/85 figure 45. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package outline (1) figure 46. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 a1 l1 l k c b ccc c a1 a2 a c seating plane 0.25 mm gage plane e3 e1 e 12 13 24 25 48 1 36 37 pin 1 identification 5b_me 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 table 50. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0. 0531 0.0551 0.0571 b 0.170 0.220 0.270 0. 0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0. 3465 0.3543 0.3622 d1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0. 3465 0.3543 0.3622 e1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0. 0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f101x8, stm32f101xb 76/85 doc id 13586 rev 13 6.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 8: general operating conditions on page 32 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ? ja ) where: t a max is the maximum ambient temperature in ? c, ? ja is the package junction-to-ambient thermal resistance, in ? c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum powe r dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 6.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org. table 51. package thermal characteristics symbol parameter value unit ? ja thermal resistance junction-ambient lqfp 100 - 14 x 14 mm / 0.5 mm pitch 46 c/w thermal resistance junction-ambient lqfp 64 - 10 x 10 mm / 0.5 mm pitch 45 thermal resistance junction-ambient lqfp 48 - 7 x 7 mm / 0.5 mm pitch 55 thermal resistance junction-ambient vfqfpn 48 - 6 x 6 mm / 0.5 mm pitch 16 thermal resistance junction-ambient vfqfpn 36 - 6 x 6 mm / 0.5 mm pitch 18
stm32f101x8, stm32f101xb package characteristics doc id 13586 rev 13 77/85 6.2.2 evaluating the maximum junct ion temperature for an application when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 52: ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. here, only temperature range 6 is available (?40 to 85 c). the following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the stm32f101xx junction temperature range. example: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output mode at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in ta b l e 5 1 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 82 c + (45 c/w 447 mw) = 82 c + 20.1 c = 102.1 c this is within the junction temperature range of the stm32f101xx (?40 < t j < 105 c). figure 47. lqfp64 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 t a (c) p d (mw) suffix 6
ordering information scheme stm32f101x8, stm32f101xb 78/85 doc id 13586 rev 13 7 ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 52. ordering information scheme example: stm32 f 101 c 8 t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 101 = access line pin count t = 36 pins c = 48 pins r = 64 pins v = 100 pins flash memory size (1) 1. although stm32f101x6 devices are no t described in this datasheet, or derable part numbers that do not show the a internal code after te mperature range code 6 should be refe rred to this datasheet for the electrical charac teristics. the low-density datasheet only cove rs stm32f101x6 devices that feature the a code. 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory package t = lqfp u = vfqfpn temperature range 6 = industrial temperature range, ?40 to 85 c. options xxx = programmed parts tr = tape and real
stm32f101x8, stm32f101xb revision history doc id 13586 rev 13 79/85 8 revision history table 53. document revision history date revision changes 06-jun-2007 1 first draft. 20-jul-07 2 i dd values modified in table 11: maximum current consumption in run and sleep modes (ta = 85 c) . v bat range modified in power supply schemes . v ref+ min value, t stab , t lat and f trig added to table 41: adc characteristics . table 37: timx characteristics modified. note 6 modified and note 8 , note 5 and note 7 added below ta b l e 4 : medium-density stm32f101xx pin definitions . figure 20: low-speed external clock source ac timing diagram , figure 11: power supply scheme , figure 28: recommended nrst pin protection and figure 29: i2c bus ac waveforms and measurement circuit(1) modified. sample size modified and machine model removed in electrostatic discharge (esd) . number of parts modified and standard reference updated in static latch-up . 25 c and 85 c conditions removed and class name modified in table 32: electrical sensitivities . t su(lse) changed to t su(lse) in table 21: hse 4-16 mhz oscillator characteristics . in table 28: flash memory endurance and data retention , typical endurance added, data retention for t a = 25 c removed and data retention for t a = 85 c added. note removed below ta b l e 8 : g e n e r a l operating conditions . v bg changed to v refint in table 11: embedded internal reference voltage . i dd max values added to table 11: maximum current consumption in run and sleep modes (ta = 85 c) . i dd(hsi) max value added to table 23: hsi oscillator characteristics . r pu and r pd min and max values added to table 33: i/o static characteristics . r pu min and max values added to table 36: nrst pin characteristics (two notes removed). datasheet title corrected. usb ch aracteristics section removed. features on page 1 list optimized. small text changes.
revision history stm32f101x8, stm32f101xb 80/85 doc id 13586 rev 13 18-oct-2007 3 v esd(cdm) value added to table 31: esd absolute maximum ratings . note added below table 10: embedded reset and power control block characteristics . and below table 21: hse 4-16 mhz oscillator characteristics . note added below table 34: output voltage characteristics and v oh parameter description modified. table 41: adc characteristics and table 43: adc accuracy - limited test conditions modified. figure 33: adc accuracy characteristics modified. packages are ecopack? compliant. tables modified in section 5.3.5: supply current characteristics . adc and anti_tamper signal names modified (see table 4: medium- density stm32f101xx pin definitions ). table 4: medium-density stm32f101xx pin definitions modified. note 4 removed and values updated in table 21: typical current consumption in standby mode . v hys modified in table 33: i/o static characteristics . updated: table 29: ems characteristics and ta b l e 3 0 : e m i characteristics . t vdd modified in table 9: operating conditions at power-up / power- down . typical values modified, note 2 modified and note 3 removed in ta b l e 2 5 : low-power mode wakeup timings . maximum current consumption ta b l e 1 2 , ta b l e 1 3 and ta b l e 1 4 updated. values added and notes added in ta b l e 1 5 : ty p i c a l a n d m a x i m u m current consumptions in stop and standby modes . on-chip peripheral current consumption on page 43 added. package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see section 6: package characteristics ). v prog added to table 27: flash memory characteristics . t s_temp added to table 45: ts characteristics . t s_vrefint added to table 11: embedded internal reference voltage . handling of unused pins specified in general input/output characteristics on page 52 . all i/os are cmos and ttl compliant. table 4: medium-density stm32f101xx pin definitions : table clarified and note 7 modified. internal lsi rc frequency changed from 32 to 40 khz (see ta b l e 2 4 : l s i oscillator characteristics ). values added to table 25: low-power mode wakeup timings . n end modified in table 28: flash memory endurance and data retention . option byte addresses corrected in figure 8: memory map . acc hsi modified in table 23: hsi oscillator characteristics . t jitter removed from table 26: pll characteristics . appendix a: important notes on page 71 added. added: figure 13 , figure 14 , figure 16 and figure 18 . table 53. document revision history (continued) date revision changes
stm32f101x8, stm32f101xb revision history doc id 13586 rev 13 81/85 22-nov-2007 4 document status promoted from preliminary data to datasheet. small text changes. stm32f101cb part number corrected in table 1: device summary . number of communication peripherals corrected for stm32f101tx in table 2: device features and peripheral counts (stm32f101xx medium- density access line) and number of gpios corrected for lqfp package. power supply schemes on page 16 modified. main function and default alternate function modified for pc14 and pc15 in table 4: medium-density stm32f101xx pin definitions , note 6 added, remap column added. figure 11: power supply scheme modified. v dd ?? v ss ratings modified and note 1 modified in table 5: voltage characteristics . note 1 modified in table 6: current characteristics . note 2 added in table 10: embedded reset and power control block characteristics . 48 and 72 mhz frequencies removed from ta b l e 1 2 , ta b l e 1 3 and ta b l e 1 4 . mcu ?s operating c onditions modified in typical current consumption on page 41 . i dd_vbat typical value at 2.4 v modified and i dd_vbat maximum value added in table 15: typical and maximum current consumptions in stop and standby modes . note added in table 16 on page 41 and ta b l e 1 7 on page 42 . table 18: peripheral current consumption modified. figure 17: typical current consumptio n in stop mode with regulator in low-power mode versus temperature at vdd = 3.3 v and 3.6 v added. note removed below figure 30: spi timing diagram - slave mode and cpha = 0 . note added below figure 31: spi timing diagram - slave mode and cpha = 1(1) . figure 34: typical connection diagram using the adc modified. t su(hse) and t su(lse) conditions modified in ta b l e 2 1 and ta b l e 2 2 , respectively. maximum values removed from table 25: low-power mode wakeup timings . t ret conditions modified in table 28: flash memory endurance and data retention . conditions modified in table 29: ems characteristics . impedance size specified in a.4: voltage glitch on adc input 0 on page 71 . small text changes in table 34: output voltage characteristics . section 5.3.11: absolute maximum ratings (electrical sensitivity) updated. details on unused pins removed from general input/output characteristics on page 52 . table 40: spi characteristics updated. notes added and i lkg removed in table 41: adc characteristics . note added in ta bl e 4 2 and ta bl e 4 5 . note 3 and note 2 added below table 43: adc accuracy - limited test conditions . avg_slope and v 25 modified in table 45: ts characteristics . ? ja value for vfqfpn36 package added in table 51: package thermal characteristics ?? i2c interface characteristics on page 59 modified. order codes replaced by section 7: ordering information scheme . table 53. document revision history (continued) date revision changes
revision history stm32f101x8, stm32f101xb 82/85 doc id 13586 rev 13 14-mar-2008 5 figure 2: clock tree on page 13 added. crc added (see crc (cyclic redundancy check) calculation unit on page 9 and figure 8: memory map on page 28 for address). maximum t j value given in table 7: thermal characteristics on page 32 . p d , t a and t j added, t prog values modified and t prog description clarified in table 27: flash memory characteristics on page 49 . i dd modified in table 15: typical and maximum current consumptions in stop and standby modes on page 38 . acc hsi modified in table 23: hsi oscillator characteristics on page 48 , note 2 removed. t ret modified in table 28: flash memory endurance and data retention . v nf(nrst) unit corrected in table 36: nrst pin characteristics on page 58 . table 40: spi characteristics on page 62 modified. i vref added in table 41: adc characteristics on page 65 . table 43: adc accuracy - limited test conditions added. table 44: adc accuracy modified. lqfp100 package specifications updated (see section 6: package characteristics on page 70 ). recommended lqfp100, lqfp64, lq fp48 and vfqfpn36 footprints added (see figure 42 , figure 44 , figure 46 and figure 40 ). section 6.2: thermal characteristics on page 76 modified. appendix a: important notes removed. 21-mar-2008 6 small text changes. in table 28: flash memory endurance and data retention : ?n end tested over the whole temperature range ? cycling conditions specified for t ret ?t ret min modified at t a = 55 c figure 2: clock tree corrected. figure 8: memory map clarified. v 25 , avg_slope and t l modified in table 45: ts characteristics . crc feature removed. 22-may-2008 7 section 1: introduction modified, section 2.2: full compatibility throughout the family added. crc feature added. i dd_vbat removed from table 21: typical current consumption in standby mode on page 42 . values added to table 39: scl frequency (fpclk1= 36 mhz, vdd = 3.3 v) on page 61 . figure 30: spi timing diagram - slave mode and cpha = 0 on page 63 modified. equation 1 corrected. section 6.2.2: evaluating the maximum junction temperature for an application on page 77 added. axx option added to table 52: ordering information scheme on page 78 . table 53. document revision history (continued) date revision changes
stm32f101x8, stm32f101xb revision history doc id 13586 rev 13 83/85 21-jul-2008 8 small text changes. power supply supervisor on page 16 modified and v dda added to table 8: general operating conditions on page 32 . capacitance modified in figure 11: power supply scheme on page 30 . table notes revised in section 5: electrical characteristics . maximum value of t rsttempo modified in table 10: embedded reset and power control block characteristics on page 34 . values added to table 15: typical and maximum current consumptions in stop and standby modes and table 21: typical current consumption in standby mode removed. f hse_ext modified in table 19: high-speed external user clock characteristics on page 44 . f pll_in modified in table 26: pll characteristics on page 49 . f hclk corrected in table 29: ems characteristics . minimum sda and scl fall time value for fast mode removed from table 38: i2c characteristics on page 60 , note 1 modified. t h(nss) modified in table 40: spi characteristics on page 62 and figure 30: spi timing diagram - slave mode and cpha = 0 on page 63 . c adc modified in table 41: adc characteristics on page 65 and figure 34: typical connection diagram using the adc modified. f pclk2 corrected in table 43: adc accuracy - limited test conditions and table 44: adc accuracy . typical t s_temp value removed from table 45: ts characteristics on page 69 . lqfp48 package specifications updated (see ta b l e 5 0 , ta b l e 4 5 and ta b l e 4 6 ). axx option removed from table 52: ordering information scheme on page 78 . 24-jul-2008 9 first page modified: ?up to 2 x i2c interfaces? instead of ?1 x i2c interface? 23-sep-2008 10 stm32f101xx devices with 32 kbyte flash memory capacity removed, document updated accordingly. section 2.2: full compatibility throughout the family on page 14 updated. notes modified in table 4: medium-density stm 32f101xx pin definitions on page 24 . note 2 modified below table 5: voltage characteristics on page 31 , | ? v ddx | min and | ? v ddx | min removed. note 2 added to table 8: general operating conditions on page 32 . measurement conditions specified in section 5.3.5: supply current characteristics on page 35 . i dd in standby mode at 85 c modified in ta b l e 1 5 : ty p i c a l a n d m a x i m u m current consumptions in stop and standby modes on page 38 . general input/output characteristics on page 52 modified. note added below table 52: ordering information scheme . section 7.1: future family enhancements removed. small text changes. table 53. document revision history (continued) date revision changes
revision history stm32f101x8, stm32f101xb 84/85 doc id 13586 rev 13 21-apr-2009 11 i/o information clarified on page 1 . figure 8: memory map modified. in table 4: medium-density stm32f101xx pin definitions : pb4, pb13, pb14, pb15, pb3/traceswo moved fr om default column to remap column. note modified in table 12: maximum current consumption in run mode, code with data processing running from flash and table 14: maximum current consumption in sleep mode, code running from flash or ram . figure 16 , figure 17 and figure 18 show typical curves. table 19: high-speed external user clock characteristics and ta bl e 2 0 : low-speed external user clock characteristics modified. acc hsi max values modified in table 23: hsi oscillator characteristics . small text changes. 22-sep-2009 12 note 5 updated and note 4 added in table 4: medium-density stm32f101xx pin definitions . v rerint and t coeff added to table 11: embedded internal reference voltage . typical i dd_vbat value added in table 15: typical and maximum current consumptions in stop and standby modes . figure 15: typical current consumption on vbat with rtc on versus temperature at different vbat values added. f hse_ext min modified in table 19: high-speed external user clock characteristics . c l1 and c l2 replaced by c in table 21: hse 4-16 mhz oscillator characteristics and table 22: lse oscillator characteristics (flse = 32.768 khz) , notes modified and moved below the tables. table 23: hsi oscillator characteristics modified. conditions removed from table 25: low-power mode wakeup timings . figure 28: recommended nrst pin protection modified. note 1 modified below figure 21: typical application with an 8 mhz crystal . figure 28: recommended nrst pin protection modified. iec 1000 standard updated to iec 61000 and sae j1752/3 updated to iec 61967-2 in section 5.3.10: emc characteristics on page 50 . jitter added to table 26: pll characteristics . c adc and r ain parameters modified in table 41: adc characteristics . r ain max values modified in table 42: rain max for fadc = 14 mhz . small text changes. 20-may-2010 13 added stm32f101tb devices. added vfqfpn48 package. updated note 2 below table 38: i2c characteristics updated figure 29: i2c bus ac waveforms and measurement circuit(1) updated figure 28: recommended nrst pin protection updated section 5.3.12: i/o port characteristics table 53. document revision history (continued) date revision changes
stm32f101x8, stm32f101xb doc id 13586 rev 13 85/85 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STM32F101VBT6XXX

	To Download STM32F101VBT6XXX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .